1. Technical Field
The embodiment described herein relates to a semiconductor apparatus, particularly, technology for generating a DLL clock signal.
2. Related Art
Semiconductor apparatuses operate in synchronization with reference periodic pulse signals, such as clocks, to improve operational speed and achieve an efficient internal operation. Therefore, most semiconductor apparatuses operate, using clocks supplied from the outside or, if needed, internal clocks generated inside.
Meanwhile, since the external clock signals that are inputted to the semiconductor apparatuses are delayed in the semiconductor apparatuses, outputting data using the delayed clock signals causes a problem that the outputted data do not synchronize with external clock signals. Therefore, the semiconductor apparatuses compensate for skew between an internal clock signal and an external clock signal, using a DLL (Delay locked Loop) or a PLL (Phase Locked Loop).
FIG. 1 is a timing diagram illustrating an operation of outputting data, using DLL clock signals generated from a DLL.
Referring to FIG. 1, a DLL clock signal ‘DLL CLOCK’ is a signal generated by compensating an external clock signal ‘INPUT CLOCK’ as much as the amount delayed in a semiconductor apparatus. That is, the phase of the DLL clock signal ‘DLL CLOCK’ is advanced by reflecting the internal delayed amount. Therefore, data ‘OUTPUT DATA’ that is outputted in synchronization with a clock signal “OUTPUT CLOCK’ transmitted to a data output circuit through an internal clock transmission path is exactly synchronized with an external clock signal ‘INPUT CLOCK’.
As described above, the DLL clock signal is used in a data output mode for outputting data; however, conventional semiconductor apparatuses still generates DLL clock signals even in modes other than a data output mode. Accordingly, current is wasted and a technology for removing this problem is needed.